There is known a transistor storage (U.S. Pat. No. 4,004,281 of 1977) wherein information is read from two columns of a matrix of memory cells with different addresses.
The storage comprises a memory cell matrix, address decoders, write circuits and read amplifiers. Each of the memory cells comprises a storage element, a write circuit, and two separate read circuits. The storage under review is disadvantageous in that it comprises much hardware and occupies a large area on the integrated circuit chip. This puts a limitation on the functional integration of the chip.
From the technical standpoint, the closest prototype of the present invention is a storage (cf. Electronica, 1974, vol. 47, No. 5, pp. 37-41) wherein information is read off one column of a memory cell matrix, and write and read circuits are combined in a single memory cell. The storage comprises two multidigit paraphase data buses and memory cells combined into a matrix.
Each line of memory cells is connected to paraphase buses of its own. Each of the memory cells comprises a storage cell and two induced channel transistors. The drains of the transistors are electrically coupled to paraphase inputs/outputs of the storage element, while their sources are connected to their respective paraphase data buses. The storage further contains write circuits and read amplifiers. Outputs of each write circuit and first inputs of each read amplifier are connected to their paraphase buses. A first input of each write circuit and an output of each read amplifier are connected to an information input and to output buses of the storage. Second and third inputs of each write circuit are connected to a write bus and a read bus, respectively. The storage further contains a decoder whose address inputs are connected to an address bus of the storage and outputs are connected to the gates of the induced channel transistors of the respective column of memory cells. This storage contains much less hardware than the one according to U.S. Pat. No. 4,004,281.
However, this storage does provide for reading information from two columns of a matrix of memory cells with different addresses. Such a capability is necessary in a microprocessor register, bearing in mind that two numbers are transmitted to the inputs of the arithmetic-logic unit of the microprocessor, and that the operation results in a single number. Successive readout of two numbers reduces the operating speed of the storage by 37.5 to 50 per cent.